The present disclosure relates to semiconductor device fabrication, and more specifically, to a replacement metal gate (RMG) and methods of forming the RMG, including forming a second tungsten region from a first tungsten region, i.e., tungsten seed layer.
Conventional integrated circuit (IC) (i.e., chip) formation generally occurs on the surface of a semiconductor substrate, e.g., silicon wafer. ICs may include a variety of interconnected devices such as resistors, transistors, capacitors, etc., formed on the surface of the semiconductor substrate. For example, an IC may include a metal-oxide-semiconductor (MOS) transistor which includes a polysilicon gate electrode. Although the use of polysilicon materials for the gate electrodes has its benefits (e.g., tolerating high temperature processing, facilitating the formation of self-aligned source and drain structures, etc.), the high resistivity of the materials results in gate electrodes which operate at slower speeds as compared to gates made of materials such as metal. One conventional method for improving the speed of the gate electrodes while also continuing to enjoy the benefits of polysilicon materials includes forming a disposable polysilicon gate for use during high temperature processing, and subsequently replacing the polysilicon gate with a lower resistance metal gate using a replacement metal gate (RMG) process.
As IC dimensions shrink, materials with lower resistivity such as tungsten (W) are utilized for replacements gates in RMG processes in order to account for the increased gate resistance associated with the dimension reduction of the gate. One challenge associated with incorporating lower resistance metals such as tungsten (W) in an RMG process may include damage to the low resistance metal caused during the RMG process. Turning to the figures, FIG. 1 shows a semiconductor structure 100 including a dielectric layer 106 on a substrate 102. Substrate 102 may include doped source/drain regions 104, and dielectric layer 106 may include a trench 108. Semiconductor structure 100 also includes a variety of structures formed in trench 108, including a work function metal (WFM) layer 110, a liner 112, a tungsten (W) gate 114, and a cap 116. During conventional processing, portions 118, 120 (in phantom) of liner 112 and tungsten gate 114, respectively, are removed to expose an upper surface 122 of WFM layer 110 positioned below an upper surface 126 of dielectric layer 106. Portions 118, 120 may be removed, for example, to allow cap 116 to be formed within trench 108. Cap 116 may then be formed on the WFM layer, liner and tungsten gate in trench 108. Portions 118, 120 of liner and tungsten gate may be removed, for example, by a chemical-mechanical planarization (CMP) process for planarization, and a reactive ion etching (RIE) process for removing the remainder of portions 118,120. The removal of portion 120 of tungsten gate 114 by CMP and/or RIE may render the semiconductor device inoperable. For example, removal of portion 120 may physically damage the tungsten gate, increase the resistivity of the tungsten gate, and/or cause non-uniformities between tungsten gates across the semiconductor structure.